Circuits which multiply two numbers and sum or accumulate the resulting product with a third number are widely used in signal processing. A typical application of a multiplier/accumulator is the implementation of a finite impulse response (FIR) digital filter which sums N products to obtain a sample value at a predetermined time, where N is an integer. A primary objective in performing multiplications and accumulations is to accomplish the mathematical calculation as quickly as possible. However, an increase in speed typically involves an increase in the amount of circuitry and irregularity of structure. Various attempts to increase the speed of an array multiplier have been made. Stylianos Pezaris in an article entitled "A 40-ns 17-Bit by 17-Bit Array Multiplier" in IEEE Transactions on Computers, Vol. C-20, No. 4, April 1971, pp. 442-447, teaches the reduction of propagation path delays by using carry-save adders modified by a "sum skip" arrangement to speed up vertical propagation of sum signals in an array multiplier. Since the Lincoln multiplier is a conventional multiplier, N rows of adders are required for an N-bit by N-bit multiplier to implement a multiplication in a conventional carry save scheme. Others have skipped both sum and carry signals over alternate rows of adders in a multiplier array as taught by Iwamura et al. in "A 16-Bit CMOS/SOS Multiplier-Accumulator" in IEEE International Conference on Circuits and Computers, Sept. 29, 1982, pp. 151-154. Iwamura et al. describe on page 151 of the above noted article a multiplier which utilizes a row skipping technique of carry and sum signals. The skipping technique is used with a conventional array multiplier rather than other methods such as Wallace's tree or Booth's method because of the complicated interconnections and irregularity of structure associated with these other methods. However, by skipping carry and sum signals over the next row, the array is effectively divided into two separate arrays, each of which provides a sum and a carry accumulation. At the bottom of the array, two combining rows of adders (not shown by Iwamura et al.) are required. The combining rows reduce the four outputs (two sums and two carrys) of the separate accumulator paths to two outputs (one sum and one carry) for carry propagation in a final row. A final row of carry look ahead adders is required to provide the output product. As stated by Iwamura et al., this method is used instead of techniques such as Booth's method or Wallace's tree because of the complicated interconnections and poor structural regularity of the latter scheme. A disadvantage with the multiplier taught by Iwamura et al. is that two rows of combining adders are required, thereby creating additional propagation delays.
Hartring et al. in an article entitled "High-Speed Low-Power Silicon MESFET Parallel Multipliers" in IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 1, February 1982, pp. 69-73, teach the use of a conventional array multiplier using a systematic carry-save adder scheme. Speed is improved by utilizing both positive and negative logic properties of full adders to provide inverting multiplier cells. Hartring et al. teach the use of a combinatorial multiplier over other methods such as modified Booth's algorithm and the Wallace scheme because the latter methods are slower and less systematic in structure.